Power semiconductor devices are widely used to carry large currents and support high voltages. One widely used power device is the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In a power MOSFET, a control signal is supplied to a gate electrode that is separated from a semiconductor surface by an intervening insulator, which may be, but is not limited to, silicon dioxide. Current conduction occurs via transport of majority carriers, without the presence of minority carrier injection that is used in bipolar transistor operation. Power MOSFETs can provide an excellent safe operating area, and can be paralleled in a unit cell structure.
As is well known to those having skill in the art, MOSFET devices may generally have a lateral structure or a vertical structure. In a lateral structure, the drain, gate and source terminals are on the same surface of a substrate. In contrast, in a vertical structure, the source and drain are on opposite surfaces of the substrate.
Although most power devices are formed in silicon, recent development efforts have also included investigation of the use of silicon carbide (SiC) for power devices. Silicon carbide has a combination of electrical and physical properties that make it an attractive semiconductor material for high temperature, high voltage, high frequency and/or high power electronic devices. These properties include a 3.0 eV bandgap, a 4 MV/cm electric field breakdown, a 4.9 W/cm-K thermal conductivity, and a 2.0×107 cm/s electron drift velocity.
These properties may allow silicon carbide power devices to operate at higher temperatures, higher power levels and/or with lower specific on-resistance than conventional silicon-based power devices. A power MOSFET fabricated in silicon carbide is described in U.S. Pat. No. 5,506,421 to Palmour entitled “Power MOSFET in Silicon Carbide” and assigned to the assignee of the present invention.
A conventional vertical power MOSFET structure 10 is illustrated in FIG. 1. The structure includes an n+ substrate 22 on which an n− drift layer 24 is formed. P-type body regions 16 are formed in the n− drift layer by, for example, ion implantation. N-type source regions 20 are formed in the body regions 16 adjacent p+ body contact regions 18. A gate insulator 28 is formed on the surface of the drift layer 24 and extends over the surface of the body regions 16 between the source regions 20 and the drift layer 24. A gate contact 26 is formed on the gate insulator 28. Source contacts 30 are formed on the source regions 20, while a drain contact 32 is formed on the substrate 22. When a sufficient voltage is applied to the gate contact 26, a channel is induced at the surface of the device 10 in the body regions 16 between the source regions 20 and the drain region 24, placing the device in an ON-state.
In the OFF state (i.e. when a gate voltage sufficient to induce a channel is not present), the power MOSFET structure 10 is equivalent to a PIN diode formed by the p+ body region 16, the n-type drift layer 24 and the n+ substrate 22. When this structure is reverse-biased, a depletion region extends principally on the drift layer side of the junction J1 between the body region 16 and the drift layer 24 towards the substrate 22, blocking the drain voltage.
However, when the device 10 is in the ON state, the drift layer 24 provides a conduction path between the source 20 and the substrate 22. Thus, the resistance of the drift layer 24 contributes to the drain-to-source resistance RDSon of the device 10.
The doping level and the thickness of the n− drift layer 24 affect both the breakdown voltage and the RDSon of the transistor device 10. The thicker the drift layer 24 and the lower its doping level, the higher the breakdown voltage of the device 10. Conversely, the thinner the drift layer 24 and the higher its doping level, the lower the RDSon (and therefore the lower the conduction losses of the device 10). Therefore, there is a trade-off between the voltage rating of a power MOSFET device and its ON-state resistance.
Typical applications for switching power devices, such as insulated gate bipolar transistors (IGBTs) and/or power MOSFETs, may benefit from reverse conduction for rectification and/or clamping by an internal and/or external diode. Because power MOSFETs have an inherent PIN diode within the structure, this internal diode may be utilized for rectification and clamping, or may be bypassed by an external diode. Because the inherent internal PIN diode of a power MOSFET may cause minority carrier injection across the drain-body junction J1, the device may have a slow reverse recovery time due to minority carrier recombination. Furthermore, injection of minority carriers across the drain-body junction J1 may contribute to degradation of the SiC crystal forming the drift layer 24.
Power switching semiconductor devices also include high voltage silicon carbide Schottky diodes and PIN diodes, which may have voltage blocking ratings between, for example, about 600V and about 10 kV or more. Such diodes may handle as much as about 100 A or more of forward current, depending on their active area design.
PIN devices, which are minority carrier devices, typically exhibit relatively poor switching speeds. In contrast, Schottky devices are theoretically capable of much higher switching speeds. In addition, silicon carbide devices may be capable of handling a higher current density than silicon devices.
A conventional SiC Schottky diode structure has an n-type SiC substrate on which an n− epitaxial layer, which functions as a drift region, is formed. The device typically includes a Schottky contact formed directly on the n− layer. A junction termination region, such as a guard ring and/or p-type JTE (unction termination extension) region, is typically formed to surround the Schottky junction active region. The purpose of junction termination region is to reduce or prevent electric field crowding at the edges of the Schottky junction, and to hinder the depletion region from interacting with the surface of the device. Surface effects may cause the depletion region to spread unevenly, which may adversely affect the breakdown voltage of the device.
Regardless of the type of termination used, the Schottky diode will break down if a large enough reverse voltage is applied to the junction. Such break downs are generally catastrophic, and may damage or destroy the device. Furthermore, even before the junction has failed, a Schottky diode may experience large reverse leakage currents. In order to reduce such leakage currents, the junction barrier Schottky (JBS) diode was developed. JBS diodes are sometimes referred to as Merged PIN—Schottky (MPS) diodes to reflect the possible mode of operation including minority carrier injection from the inherent PiN diode within the JBS structure.
A conventional JBS diode 50 is illustrated in FIG. 2. As shown therein, a conventional JBS diode 50 includes an n-type substrate 52 on which an n− drift layer 54 is formed. A plurality of p+ regions 56 are formed, typically by ion implantation, in the surface of the n− drift layer 54. A metal anode contact 58 is formed on the surface of the n− drift layer 54 in contact with both the n− drift layer 54 and the p+ regions 56. The anode contact 58 forms a Schottky junction with the exposed portions of the drift layer 54 between the p+ regions 56, and may form an ohmic contact with the p+ regions 56. A cathode contact 60 is formed on the substrate 52. Silicon carbide-based JBS diodes are described, for example, in U.S. Pat. Nos. 6,104,043 and 6,524,900.
In forward operation, the junction J3 between the anode contact 58 and the drift layer 54 turns on at lower voltages than the junction J2 between the p+ regions 56 and the drift layer 54. Thus, at low forward voltages, the device exhibits Schottky diode behavior. That is, current transport in the device is dominated by majority carriers (electrons) injected across the Schottky junction J3 at low forward voltages. As there may be no minority carrier injection (and thus no minority charge storage) in the device at normal operating voltages, JBS diodes may have fast switching speeds characteristic of Schottky diodes.
Under reverse bias conditions, however, the depletion regions formed by the PN junctions J2 between the p+ regions 56 and the drift layer 54 expand to block reverse current through the device 50, protecting the Schottky junction J3 and limiting reverse leakage current in the device 50. Thus, in reverse bias, the JBS diode 50 approaches the voltage blocking behavior of a PIN diode. The voltage blocking ability of the device 50 is typically determined by the thickness and doping of the drift layer 54 and the design of the edge termination.